Field of the Invention
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits.
Description of Related Art
The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or “IoT”). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore's Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.
In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-μm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or “RF”) designers still struggle to discover how to make high-performance integrated circuits (or “ICs”) for ultra-deep sub-μm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium.
Prior Art
The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore's law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (˜18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These “mixed-mode” IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Eliminating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.
Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the “R” and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant “bias” currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.
As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving enough room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.
Prior art CMOS integrated circuit amplifiers are based on several analog or mixed-mode IC process extensions which are not available on all-digital IC processes. Primarily matched pairs of transistors are used as a differential inputs and current mirrors. These analog FET transistors must be long, as depicted in FIG. 1q, to provide the necessary high output resistance, and also must be wide in order to support the necessary current that is mirrored between them. For example, conduction channel 13q which is operable by the gate terminal 17q must have a sufficient length or distance between the source terminal 14q and the drain terminal 19q on the body/substrate 16q. Bias currents, which are normally larger than the peak analog signal currents, must be generated and maintained. Resistors and large area capacitors are normally required to create references and stabilize the amplifiers. Because of parametric sensitivity, these designs are not very portable between IC processes or venders. They are redesigned for each IC process node and are very specifically tailored to their various applications. Due to their bulkiness amplifiers are normally the limiting speed element of an IC system. What is needed is a scalable design that uses logic-only IC processes components, is process parameter tolerant, consumes a small area, uses relatively low power, and operates at voltages significantly below 1 volt. This is the subject of the present invention.
The conventional MOS amplifier gain formation is an input voltage driving a trans-conductance (gm) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The resulting amplifier voltage gain is gm*Rload. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high, and the voltage gain high, these parallel transistors must be very long, but to drive enough current, these transistors must be very wide to carry sufficient current also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drives is also an additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifiers output resistance, modifying the AC performance characteristics. What is actually needed is exactly the opposite of the present analog amplifier operating principles of very small voltage-input to high-impedance current-output (gm); which the present invention is about: very small current-input to low-impedance voltage-output (rm). FIG. 1a is a transistor level schematic diagram of a high-quality MOS IC OpAmp as a baseline reference (Gray, Paul R. et al., “Analysis and Design of Analog Integrated Circuits,” 5th edition, John Wiley & Son Ltd, at pg. 484) which is used for comparison in the description of the amplifiers illustrated herein.
The baseline comparisons are (all made in a 180 nm IC process) in the form of performance plots as in: a Bode Gain-Phase plot FIG. 1b, when Vdd=1.8 Volts and Rcmp=700 ohms. Wherever possible all the axis scales for each of these three comparison plots are kept the same. A 180 nm process was selected for comparison of all the comparative examples in this specification because conventional prior art amplifiers work best and have had the most usage to mature the analog mixed-mode IC process extensions offered as required for conventional analog. Also as the IC process is shrunk and the power supply voltage is decreased, this is where the implementations of the present invention become highly beneficial.
Normally MOS amplifiers operate within a square-law form due to the strong-inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the “moderate-inversion” transition between these two operating mode provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about fast amplifiers that operate in the exponential mode but not in weak-inversion; instead a super-saturated mode is introduced.
To understand the prior art, let's begin with a discussion of weak vs. strong-inversion (Enz, Christian C. et al., “Charge-based MOS Transistor Modeling—The EKV model for low-power and RF IC Design, John Wiley & Son Ltd., 2006). Referring to FIGS. 1e and 1f, weak-inversion is the range where most designers would consider the transistor to be OFF:                Weak conduction channel inversion 13e occurs when the Gate 17e on the body/substrate 16e is operated below its threshold voltage Vthreshold 17f in FIG. 1f with channel ionization 13e characterized by a thin surface layer;        Source 14e to Drain 19e voltage 19f is small (typically less than 100 mV);        For weak-inversion, the gate G 17e is typically operated by gate voltage supply 12e at a low potential (˜300 mV);        This creates a channel surface conduction layer 13e, of uniform depth from source S 14e to drain D 19e;         Since there is essentially zero voltage gradient along the channel 13e (˜no electric field), any current between drain D 19e and source S 14e is primarily supported by diffusion;        Increased gate voltage Vgs 12e at the gate G 17e increases the thickness of the conduction layer 13e below the gate 17e, thus allowing more charge to diffuse along the channel 13e;         The conductivity of this surface layer is exponentially related to the gate voltage Vgs 12e at the gate G 17e;         This exponential relationship holds over as many as 6 decades of dynamic analog signal range for the drain channel current;        The channel appears as a moderately high value resistor for its channel current (many 100+s of K-Ohms);        The resulting uniform conduction channel depth promotes higher exponential gain but at a severe speed penalty due to low current density; and        This weak-inversion conduction is reflected in a near zero operating point 13f in FIG. 1f.         
Strong conduction channel inversion occurs when the gate voltage Vgs 12g at the Gate 17g on the body/substrate 16g is operated above its threshold voltage 17h (referring to FIGS. 1g and 1h) with channel ionization characterized by a graduated conduction channel, deeper near the Source 14g and shallow near at the Drain 19g:                 Strong conduction channel inversion 15g and 15h occurs when the Drain 19g to Source 14g voltage 19h is larger than the threshold Vthreshold 17h in FIG. 1h (typically in excess of 400 mV);        The Gate 17g is operated above its threshold voltage Vthreshold 17h in FIG. 1h;         In strong-inversion 18g, the Drain 19g voltage is typically operated above the Gate 17g voltage which results in a pinched-off conduction channel 15g near the Drain 19g;         This pinched-off channel at 15g gives rise to high output impedance at the Drain 19g and can be observed as the thick flat part 18h of the operating characteristic plot FIG. 1h;         As the Drain 19g voltage Vd is changed, the pinched-off region 15g changes length, but its thin conduction layer is retained, keeping the output impedance high;        Due to the Gate 17g to channel 15g voltage and the electric field along the conduction channel path (Drain 19g to Source 14g), the conduction channel 15g is forced deeper at the Source 14g and tapers to near pinch-off at the Drain 19g;         The resulting conduction layer behaves with a Square-law response to the gate voltage at the Gate 17g;         In strong-inversion, dynamic range of channel current is limited to about 2 or 3 decades; the channel must drop into weak-inversion for additional dynamic range;        This strong-inversion conduction channel 15g appears as an adjustable current source (high value resistor); and        The wedge shape of the conduction channel 15g provides high speed from high current density, but requires the carriers to transit the channel and velocity saturation is reached limiting the speed or cutoff frequency of the transistor; and        This is reflected as the operating point 15h in FIG. 1h which is along its bolded line 18h.         
FIG. 1e, shows the channel development under weak-inversion conditions. The conduction channel has a relatively even distribution of carriers over its entire length and width. Note that the conduction 13e depth of the entire channel is the same as the pinch-off area 15g on the right channel side (or near the drain 19g) of FIG. 1g. The output drain voltage Vd loaded on the drain D 19e by bias current, Ibias Ld19e. This thin conduction layer 13e contributes a significant amount of noise because the channel current travels along the surface where defect traps are concentrated. The Gate 17e to channel voltage Vg in FIG. 1e has a strong (exponential) effect on the density of carriers in this conduction layer 13e. 
FIG. 1f shows a plot which has an exponential relationship of drain current Id to drain voltage Vds using a fixed gate voltage Vg. It is to be noted that the drain voltage Vds must be limited to a small value (on the order of 100 mV) in order to stay in weak-inversion.
FIG. 1g shows channel 15g ionization under strong-inversion conditions. In strong-inversion, there is an output drain voltage Vd loaded on the Drain 19g by an output load: Ibias Ld19g. This load presents a lower potential difference between Gate 17g and Drain 19g end of the conduction channel 15g than the potential difference between the Gate 17g and Source 14g end of the conduction channel, resulting in a tapered conduction channel 15g. The conduction channel thins down to a minimum as it approaches the drain provide a high output resistance. This output resistance is primarily defined by the thin channel cross-sectional area. As the drain voltage is varied, this thin pinched-off length of the channel changes, but not so much its cross-sectional area. This leads to a high output resistance, in that Drain 19g output resistance variation with drain voltage is relatively small, yielding a high output resistance. This high resistance is required in conventional gm analog MOS circuit design. In this pinched-off channel region, the carriers approach their velocity saturation, thus limiting their transit time along the channel. This is called “channel length modulation” (the flat part of the channel 15g), resulting in pinch-off near the drain diffusion where the channel reaches a thin layer at 15g. The pinch-off region, where the carriers are forced to the top of the channel, imparts significant noise by means of surface defect carrier traps. The higher the drain voltage Vd, the longer the pinch-off region and thus the higher the contributed noise (Rahul, Sarpeshkar, “Ultra Low Power Bioelectronics-Fundamentals, Biomedical Applications, and Bio Inspired Systems”, ISBN9780521857277, and Lee, Thomas “The Design of CMOS Radio-Frequency Integrated Circuits”, 2nd Ed, Cambridge ISBN-13 978-0521835398), thus is desired to keep this voltage low for low noise contribution to the channel current. Other effects such as velocity saturation and hot electron jumping over to the gate oxide are noted around this thin saturated region, thus it would be highly desirable to minimize this region by lower voltage and semiconductor doping profiles.
FIG. 1h shows a characteristic plot which approaches a “constant current” relationship between drain current Id and drain voltage Vds with a fixed Gate voltage Vg on the gate G. It is to be noted that the drain voltage Vds spans a much larger range of nearly the power supply voltage Vdd, while maintaining the same current.
A two-finger CMOS inverter is illustrated in FIGS. 1i, 1j, 1k, 1m, and 1n. A logic inverter possesses several desirable properties:                They exist in all logic IC processes        are the most common and fundamental building block        highly scalable        process parameter drift tolerant        small        high speed        high output drive for varying capacitive loads        arguably the highest gain of a complementary pair of MOS transistors        low power        easily used        
A basic two finger inverter schematic of the prior art is depicted in FIG. 1i. For example, Vin 10i of the basis two finger inverter 100 is connected to the gate terminals of NFET 101 and PFET 102. The source terminal of NFET 101 is connected to negative power voltage, and the source terminal of PFET 102 is connected to positive power voltage. The drains of NFET 101 and PFET 102 are connected together to form an output 19i. A generic physical layout is illustrated in FIG. 1k in parallel with another inverter schematic diagram in FIG. 1j which has been stretched out and aligned alongside the physical layout to correlate the inverter schematic FIG. 1j to the physical layout structure FIG. 1k. Artistic liberty was used to clearly relate these two figures. Actual physical layout would be in accordance of the design rules and practices of the IC process it is designed for. FIG. 1m is a 3-D sketch of the physical layout. FIG. 1n shows a cross-section view of the physical layout as indicated Section AA in FIG. 1m. The two finger inverter 100 includes a common gate terminal 10j/10k/10m/10n, and output 19j/19k/19m/19n connected to drain terminal D− 11j/11k/11m/11n and D+12j/12k/12m/12n. As can be seen in FIGS. 1k to 1n, the drain D− 11k/11m/11n is displaced between the source terminals, S− s13k/s13m/s13n and s15k/s15m/s15n, while the drain D+ 12k/12m/12n is displaced between the source terminals, S+s16k/s16m/s16n and s14k/s14m/s14n. The pull down transistor channel 13k/13m/13n is in parallel with 15k/15m/15n, while the other pull down transistor channel 14k/14m/14n is in parallel with 16k/16m/16n. The poly transistor control gate 17k/17m/17n is in communication with the gate terminal 10k/10m/10n. Drain diffusions 12n are shown in FIG. 1n. The charge distribution in the drain channels 13n, 15n, 14n, and 16n are shown in FIG. 1n. This charge distribution is illustrated for the voltage where the logic is in the middle or most active part of its state change. This charge distribution is an extension of the charge distribution in FIG. 1g. These inverter figures are closely related to the present invention as the basis for making minor alterations that do not require any IC process modification as will be developed below.
FIG. 1p illustrates a prior art MOS structure that turns out to actually emulate a combination of both modes of operation; strong-inversion FIG. 1g, 1h with enhanced weak-inversion-like properties of FIG. 1e, 1f. This structure is inherent in a 2-finger inverter as shown twice in the FIG. 1k physical layout abstraction. For reasons that will be developed, this structure will be named an iFET (MOSFET with a current input terminal=i) where the MOS structure is employed for the present invention.
Although similar MOS structures appear in prior art, no significant exploitation of many of its unique properties are known or published. In addition, proper biasing remains as a problem(s) for its operation(s). A deeper understanding of the internal mechanisms resulted in discovery of many desirable applications (enabling superior operation at deep-sub-micron scale), including an approach to proper biasing that takes advantage of natural equilibrium. This natural equilibrium is the result of a “PTAT”/“CTAT” (proportional to absolute temperature/complement to absolute temperature) known as a “Band-Gap” voltage reference mechanism, again functional at deep-sub-micron scale.
Some references show a MOS field effect device includes a body/substrate 16p, the source terminal 14p and drain terminal 19p on the body 16p. The gate terminal 17p is placed between the source terminal 14p and the drain terminal 19p for controlling conductivity therebetween. The device further includes two identical regions 13p and 15p of like “conductivity type” separated by a diffusion region 11p(designated as Z for Low Impedance in the prior art) as shown in FIG. 1p. Non-patent literature, Pain, Bedabrata et al., “Low-power low-noise analog circuits for on-focal-plane signal processing of infrared sensors”, the Jet Propulsion Laboratory, California Institute of Technology, and the Defense Advanced Research Projects Agency and the National Aeronautics and Space Administration; and Baker, Jacob et al., “High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Design”, Boise State University, for example, shows such a structure. However, these references do not exploit any opportunities as shown in this present invention, especially when complementary devices like this are combined into a single composite device structure as will be explained in this invention. Such configurations have been called self-cascading or split-length devices. The two conduction regions of such a configuration are arranged between source and a drain diffusions and have both a high impedance common gate connection and a low impedance Z connection to the mid channel region. This low impedance mid channel control input/output Z, when exploited as outlined in this document, enables an entirely new set of analog design methods and capabilities.
Although a cascode amplifier can be found in prior art, the prior art does not contain a complementary pair of cascode transistors connected as a totem-pole. With this simple compound device structure, feedback from the output to the input can be used to self-bias the resulting inverter into its linear mode. As mentioned above in association with FIG. 1a, the biasing of an amplifier by means of current mirrors has always been problematic; however, the novel and inventive self-biasing structure of the present invention addresses such an issue. Advantages of the configuration of the present invention (referred to as a complementary iFET or CiFET) are many, including, but not limited to:                Gain of the single stage is maximum when the output is at the midpoint (self-bias point);        The gain of a single CiFET stage is high (typically approaching 100), therefore, while the final output may swing close to the rails, its input remains near the midpoint where the gain is high.        When used in a series chain of CiFET devices, all earlier stages operate with their inputs and outputs near the mid-point (“sweet-spot”) where the gain is maximized;        Slew rate and symmetry are maximized where the channel current is highest (near the mid-point);        Noise is minimized where the channel current is highest (near the mid-point); and        Parasitic effects are negligible where the voltage swing is small.        
When the gate input signal moves in one direction, the output moves in the inverse direction. For example; a positive input yields a negative output, not so much because the N-channel device is turned on harder, but rather because the P-channel device is being turned off. A Thevenin/Norton analysis perspective shows that the current through the P and N devices must be exactly the same, because there is nowhere else for drain current in one transistor to go except through the drain of the complementary transistor; however the voltage drop across those devices does not have to be equal, but must sum to the power supply voltage. Due to the super-saturated source channel, these voltages are tied together exponentially. This is even more evident at low power supply voltages where the voltage gain peaks due to the conduction channels being forced into a diffusion mode of operation similar to weak-inversion. This means that the gate-to-source voltage is precisely defined by the same and only drain current going through both transistors. Exponentials have the unique transparent physical property like as with a time constant, or “half-life;” It does not matter where a value is at a given point of time, a time constant later the value will be a fixed percentage closer to the final value. This is a “minds-eye” illustration of the primary contributor to output movement in response to input change. This same current balance of gate-to-source operating voltages also indicates why the “sweet-spot” in the self-biased amplifier is so repeatable. In effect it is used as a differential pair-like reference point to the amplifier input signal.
Briefly stated, the operation of the conventional CMOS amplifier of FIG. 1a is as follows:
In operation, differential analog input voltages are applied to Input + 10a and Input − 11a of a precisely matched pair of transistors Q1a and Q2a respectively. Any mismatch in these two transistors appears as a DC voltage added to the differential input. If there is 1 millivolt of mismatch, which is very hard to meet in CMOS, and the amplifier has a gain of 1000, the output voltage error will be 1 volt. In newer IC process nodes, power supplies are already limited to less than a volt. Exotic double centroid physical layout with multiple identical transistors arranged in diametrical opposition and everything else possible symmetrically possible are needed in the physical layout of the differential pair to minimize the offset voltage.
These amplifiers function by steering and mirroring bias currents from a current source 12a between their transistors. All the bias currents have to be larger than the peak signal deviations and these currents always flow. These currents also have to be large enough to drive the internal capacitive load of the amplifier's internal transistors plus interconnect, not to mention the output drive current which comprises the capacitive load at the maximum bandwidth frequency or slew rate.
The first bias current mirror input transistor is a transistor Q8a which is “diode connected” in that its gate and drain are tied together and bias at a threshold voltage below the top power supply rail. This bias voltage is applied to the gates of two transistors Q5a, Q7a additional positive rail based current mirrors that have to be matched to a lesser degree. In order to progressively increase the mirrored currents from the bias current mirror input transistor Q8a to the differential current feed transistor Q5a to the output pull-up current transistor Q7a, the transistors Q5a and Q7a are actually multiple instances connected in parallel. A double for the transistor Q5a and an eight (8) times for the transistor Q7a are typical choices for these multiples.
The differential pair of the transistors Q1a, Q2a is used to split the bias current to the transistor Q5a equally at the zero differential voltage input where the amplifier strives for. To achieve a voltage gain in analog designs, a positive drive current is balanced against a negative drive current. The differential pair of transistors Q1a, Q2a achieves this by mirroring transistor Q3a of the outputs back to the other leg of transistor Q4a, making current opposition with the transistor Q2a. Voltage gain is gm*RL where RL is the parallel combination of the output impedance of the transistors Q4a and Q2a. For analog MOSFET transistors to present a high impedance on their output, they need to be very long because the depilation width due to drain voltage modifies the conduction channel length near the drain terminal. This is called “channel length modulation” which is similar to the bipolar “Early voltage” named by Jim Early of Fairchild Semiconductor during the early bipolar days. For this high output impedance requirement, the transistor Q4a must be long, and it also must be equally wide to preserve its gain setting the basic transistor sizing of the amplifier. This size must be set equal for the transistors Q3a and Q6a, except the transistor Q6a must also include the multiple used for the transistors Q5a to Q7a along with a factor of two to make up for the split of current by the differential pair. In equilibrium, the gate voltage on the transistor Q6a wants to be the same as the gate voltage on the transistors Q3a, Q4a looking like a pseudo-current mirror arrangement at the bottom power supply rail.
There are still many other linear amplifier circuit design considerations beyond these basic principles like stability considerations by compensation resistance or Rcomp 15a and compensation capacitance or Ccomp 16a and power supply noise rejection. As can easily be envisioned, the design of analog circuits in an IC is quite involved, process parameter dependent, and not very portable between IC processes.
The resulting linearity of these amplifiers are also limited due to different non-linear characteristics between the gain device and the load device (pull-up and pull-down) which cannot cancel each other out. The CiFET device structure, which is the present invention to be explained later in this specification, loads itself with the same device structure, except that the combination obtains its complementary nature through the use of opposite semiconductor diffusion types which inherently and precisely mimic any non-linear characteristics with the opposite sign to cancel each other's linearity deviations out. CMOS inverters get their opposing drive through the opposite semiconductor diffusion type, thus are a good foundation to base linearity on. This is because the same current is carried through one transistor is also passed through the complementary device. Inversion is obtained through opposite diffusions.
It is to be noted that during the transition from vacuum tubes to bipolar transistors the industry underwent a major paradigm shift, learning to think in terms of current rather than voltage. With the advent of FETs & MOSFETs the pendulum swing is back toward thinking in terms of voltage, but much knowledge has been lost or forgotten. Herein is contained the rediscovery of some old ideas as well as some new ones, all applied to the up-coming “current” state of the art. It is believed that the inherent simplicity of the present invention speaks to their applicability and completeness.
A first issue may be that there is always a need for a little analog functionality, yet nearly all analog performance metrics of a MOS transistor are remarkably poor as compared to that of a Bipolar transistor. The industry has made MOS devices serve by employing extensive “work-arounds.” Conventional analog design is constrained by one or more of the followings:                Power supply voltages sufficient to bias the stacked thresholds, and transistors large enough to supply the necessary low output impedance, or high output impedance for gain and linearity.        Process extensions (unavailable at deep sub-μm scale) to function at all, let alone with the enhanced performance, demonstrated herein.        Resistors, inductors, and large capacitors are mostly non-existent for analog designs in newer IC processes.        
In contrast, bipolar transistors can be made to have high gain (β), wider bandwidth, wider dynamic range (many decades, from near the rails down to the noise floor), better matching (required in differential pairs), and band-gap references. Junction FETs, which operate with sub-surface channel conduction below the surface defects, have lower noise than bipolar transistors. Likewise the iFET super-saturated source channel operates primarily below the defects at the channel surface underneath the gate oxide.
MOS designs are poorer in the above areas but have their own extreme advantages, including, but not limited to:                MOS devices are small        highly scalable        high speed        low power        ultra-dense/high functionality systems on a chip, where Bipolar designs cannot go (deep sub-μm scale).        
Accordingly, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.
Today the real-world of analog circuit design signals still needs to be converted, on both the front and back end of signal processing systems. This need has become a road-block at deep sub-μm scale.
Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage, with a closed loop, is stable (does not oscillate). Increased loop gain requires that stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate).
The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep-sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.
There is a long felt needs for low-cost/high-performance systems on a single chip to realize, affordable high-volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices.